Clock signals for electrical devices may be constrained by a number of error sources. For example, these error sources may include delay variations among signals for a closed-loop frequency-control system (e.g., a delay-locked loop (DLL), a phase-locked loop (PLL), or a frequency-locked loop (FLL)), channel-to-channel skew, and various forms of jitter.
Various approaches to eliminate mismatch (e.g., delay or timing mismatch) between clock channels include layout techniques, providing gate delays, and trimming. However, these approaches generally provide only a coarse approximation and may not reduce mismatch to acceptable levels, especially over process, voltage, and temperature.
As a result, there is a need for improved clock techniques, which may reduce and/or control mismatch and provide improved skew control.